# (15 points) Your colleague is trying to code a VHDL model for a 7419 register. Review…

(15 points) Your colleague is trying to code a VHDL model for a 7419 register. Review the code on the next page and make any and all correction correct working model. Note the function model. Note the function table and additional information regarding need to solve this problem. DL model for a 74194 4-bit bidirectional universal shift tions that are necessary to produce a al information regarding the problem that you Control Signals Mode CirN SI SO Outputs 1 1 1 0 0 1 0 1 0 0 Q3 RSIN Q2 D3 0 0 Q2 Q Q3 Q2 Qi Qo D2 Di 0 (asynchronous clear) Qo (hold) 01 (right shift) LSIN (left shift) Do (parallel load) 1 1 1 Notes: 1. S1 and SO control the mode of the shift register as described in the table above. 2. RSIN is the bit shifted in for the right shift operation and LSIN is the bit shifted in for the left shift operation Problem grading: for each appropriate fix, you receive a point; for each lose a point, where maximum number of point mber of points awarded is 30 and the minimum awarded eive a point; for each change that introduces an error, you and the minimum awarded is 0. library IEEE; library ieee.std_logic_1164.all; library IEEE.numeric_std.all; entity e74194 is (51,50, Clrn: in std_logic; Qout: out number (3 downto 0)); end ent74194; D: in int (3 downto 0); architecture b74194 of 74194 is object Q: std_logic_vector (15 downto 0); begin process (Q, S1, S2) begin if cik’event then — change state on rising edge if ClrN – ‘1’ then — asynchronous reset Qout null; — hold when “1” => Q(3 downto 1)