4) This exercise will first present the modified algorithm for computing the product of two numbers…

4) This exercise will first present the modified algorithm for computing the product of two numbers represented in twos complement with an illustrated example and then ask you to repeat for a different number pair The hardware and the flowchart for signed multiplication in twos complement representation of binary numbers will be slightly modified as follows. Use the version of the unsigned multiplication hardware which employs one double-sized register to hold the partial product and the multiplier a. When shifting right, extend the sign of the product (which is assumed to be in H:LO register pair in a MIPS machine). b. If the multiplier is negative, the last step should be a subtract and not an add. The modified hardware and the flowchart are presented below c. Any carry out from the MSB position of the HILO register following add/subtract will be ignored if 0) both the multiplicand and multplier are negative, (i) the multiplicand is negative but the multiplier is positive. Here is the modified flowchart adapted for MIPS HI:LO register pair to hold the product: Similar to Unsigned Multiplier ALU produces a Multiplicand and Hl are result is the sign of the result Start Multiplicand 32 bits 2 bits Loroj? add, sub 33-bit ALU 33 bits 32 bits First 31 iterations: HI HI+Multiplicand Last iteration: Hl Hl- Multiplicand shift right LO Control Shift Right Product (HI, LO) 1 bit write 64 bits Loro No es Done Example Consider product of 2 signed binary numbers in twos complement representation as 1100 (multiplicand) and 1101 multiplier) where both are negative with decimal equivalents of -4 and -3, respectively The product is positive and equal to 12 in decimal and 00001100 in binary in twos complement representation Assume LO has the multiplier and Hl is initialized to zeros. Then upon first time the multiplicand is added to the Hi (partial product), the HI must be sign-extended. The shifts are arithmetic shift right: the sign bit of multiplicand is inserted from left into the HI MS8 position upon arithmetic shiftright.