I need help in multisim 1. Load the circuit E7A-1.MS7, shown in Figure 7A.1 2. 5…

I need help in multisim

1. Load the circuit E7A-1.MS7, shown in Figure 7A.1 2. 5 v 5 V 250 Hz S V INA INB QB RO1 RO2 R91 R92 7490N Figure 7A.1: 7490 decade counter The 7490 decade counter is wired internally to reset from nine back to zero. Verify that the counting sequence goes from zero to nine 2. What happens if both RO inputs are pulled high while the 7490 is counting? Demonstrate this in the circuit 3. What happens if both R9 inputs are pulled high during counting? 4. What happens if the B-CLK input is disconnected from the A output during counting? 5. View the counting sequence using the logic analyzer