If the processor produces an address which is of size 6 bits, with each block of the main memory…

If the processor produces an address which is of size 6 bits, with each block of the main memory having
the capacity to store 4 words. Answers the following with relevant calculations.
1) no. of words that can be stored in the main memory?
2) no. of blocks that would be required to store the words in main memory?
3) Block number value, along with the block offset value to access word 50?
4) no. of lines that would be required to store the main memory blocks in the cache memory?
5) If direct mapping method is to be implemented which blocks of Main Memory would be mapped
directly to line 2, provide

»If the processor produces an address which is of size 6 bits, with each block of the main memory having
the capacity to store 4 words. Answers the following with relevant calculations.
1) no. of words that can be stored in the main memory?
2) no. of blocks that would be required to store the words in main memory?
3) Block number value, along with the block offset value to access word 50?
4) no. of lines that would be required to store the main memory blocks in the cache memory?
5) If direct mapping method is to be implemented which blocks of Main Memory would be mapped
directly to line 2, provide valid reason?
6) If direct mapping method is to be implemented and line 2 is empty can word 50 be placed inside it,
provide valid reason?
7) If Associative mapping is implemented, what are the Tag, Line No and word offset values for word
50.
8) How many comparators would be required under Associative mapping to access the cache lines,
provide valid reason?
9) How many comparators would be required under 2-way Set-Associative mapping to access the cache
lines, provide valid reason?
10) In terms of Hardware implementation of mapping, which mapping would be the most expensive,
provide valid reasons?
Q P – A S M

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